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Inputs
We take your design in almost any format (VHDL, verilog, gate level netlist, ASIC layout, etc),
and convert it for use on our SMGA technology.
Design Conversion
We then optimize your design to our technology, and perform simulations to
ensure that the FPGA or old part is mimicked exactly. We can also implement design improvements and
performance upgrades at this stage.
Verification
The new netlist is mapped onto our SMGA base wafers, and timing information
is passed back to the customer for verification in SDF format.
Test Program Development
Since ASIC technology requires complete testing of each part to ensure
reliability, we develop a test program for the new ASIC, covering up to 100% of the possible
manufacturing faults.
Package and Test
Through our partners, we take care of the dicing, testing, and packaging
of the part. We support all
package form factors and qualification standards (commercial,
automotive, military, space).
Detailed Design Flow
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