Tanner Tools v. 12.1 and HiPer Verify v. 2.1

Give your designers a seamless, efficient path from design capture through verification. Tanner EDA tools for analog and mixed-signal IC design enable faster time to market, lower costs, fewer risks, and shorter cycle times. You can implement a complete, integrated design flow with Tanner EDA HiPer Silicon™.

HiPer Silicon is a complete IC design suite that covers schematic capture, circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. It can increase your productivity and speed your design concepts to silicon. HiPer Silicon includes S-Edit, T-Spice, L-Edit, and HiPer Verify. Each tool has been significantly enhanced in the past year.

S-Edit

Over the past year, S-Edit has been completely re-architected to offer performance, capacity, and features optimized for today’s designs. It is built to reduce front-end design time, which typically consumes the majority of full custom design time. With S-Edit, creating and modifying next-generation devices is much faster than in previously available analog or mixed-signal design tools. S-Edit also imports schematics from other tools such as Cadence® and ViewDraw®.

Features of the re-architected S-Edit include:

• Improved performance and scalability to very large designs.
• Integrated productivity tools such as design checker and library browser.
• Fully scriptable and expandable using TCL command language.
• Multiple language support for English, Chinese, Russian, and Japanese.
• Tight integration with SPICE simulation and waveform crossprobing.

T-Spice

T-Spice lets engineers simulate key blocks during the design process. It puts you in control of simulation jobs with an easy-to-use graphical interface and a faster, more intuitive design environment. T-Spice delivers highly accurate results by supporting the latest foundry, transistor, and behavioral models.

T-Spice includes the following new features:

• Improved speed and convergence performance with new homotopy algorithm.
• Crossprobing from S-Edit of voltages, currents, and charges, including terminal currents of subcircuits.
• Multithreaded linear solver.
• Ability to chain .MEASURE statements.
• The latest models, including BSIM4 v4.5.0 and Philips PSP MOS model.

L-Edit

L-Edit enables analog/mixed-signal designers to automate the layout of similar circuits for different ICs. It meets your needs by combining the fastest rendering available with powerful features. You can get started with minimal training, and draw and edit quickly with fewer keystrokes and mouse clicks than in other layout tools.

New features in L-Edit include:

• Layout-vs-layout comparison (LVL).
• Improved import of Virtuoso technology files.
• Enhanced Layer Palette icon filtering.
• More control over selectability of instances.
• L-Edit Curve Tools that provide the ability to chamfer or fillet objects.

HiPer Verify

 

HiPer Verify runs Calibre® and Dracula® DRC files hierarchically and natively to catch up to 95 percent of mixed-signal design rule violations early, before they become a major problem. It enables you to find and fix errors quickly by going instantly to the location of a violation and viewing a clear and thorough summary report.

New features in HiPer Verify include:

• Significantly improved performance on many layer derivations and rules.
• Addition of RECTANGLE ENCLOSE command.
• Connectivity-based DRC rules, including ERC checks such as checking for soft connections or floating wells.
• Text-based selection of polygons.

For product, pricing and licensing information please contact a Tanner representative via email at salesnw@tanner.com or +1-626-471-9701.