In an ever increasing competitive market, many businesses are finding it difficult to justify the exorbitant costs associate with so called .high-end. design systems. An increasing number of IC designers are searching for an affordable alternative to the mainstream EDA tools. At least one option exists, offering flexibility and functionality, with vendor responsiveness a welcome extra.
For leading-edge, complex, all-digital IC design, project teams have little choice but to invest in EDA tools from one of the major vendors, such as Cadence, Mentor Graphics or Synopsys. The advantages afforded by the sheer degree of automation on offer, plus the essential support for IDM and the mainstream foundry processes, far outweigh the cost of the tools. In highly competitive digital-oriented markets, the critical success factors are to deliver differentiated products, in the most advanced technologies, within tight time constraints. Tools that improve design productivity through automation and leverage design reuse methodologies are critical.
But for any other type of IC design, the dynamics change dramatically. Add a chunk of analog and mixed-signal circuitry, and the 'pushbutton' automation typical in the digital world, does not work. The design process requires considerably more engineer interaction and intervention. For designs targeted at non-mainstream technology processes, the mainstream EDA vendor tools are unlikely to provide the foundry or model support required. For companies designing a variety of such ICs, and not for production in high volumes, the total cost of ownership of tools from these vendors is unacceptably high.
Painless Migration
One project group within a large research division of a major, multinational systems house, recently successfully migrated from a full suite of the most up-to-date Cadence IC design tools to the eminently affordable toolset from Tanner EDA. The switch was carefully planned and has proved not only highly effective, but relatively painless too.
The project group, with 20 designers, typically completes five or six ICs per year, plus derivatives and variations. Containing a significant proportion, up to 80%, analogue and mixed signal circuitry, the ICs are equivalent to around 100,000 transistors in size. Target end products include displays and medical devices. These are ground-breaking designs, initially fabricated on in-house pilot lines, on processes that are also under development, to prove the concept and demonstrate a leading edge capability.
The Cadence tools had been the corporate choice for many years, used in the company's myriad design departments globally. But a change in corporate structure meant that the company was no longer a high volume user of Cadence tools. The pricing structure changed accordingly, and the cost to this design department increased beyond the point of being a viable proposition. The group had to find an alternative solution.
A small team was established to investigate the options and report back. Key selection criteria included comprehensive analogue design features, with schematic driven layout, design rule checking and detailed parasitic extraction. Another critical requirement is the ability to build and incorporate simulation models and process-specific device models.
They settled on Tanner fairly quickly as it was the only realistic, affordable possibility. Some point tools and freeware were evaluated, and while they had some interesting potential and capability, they did not provide a complete solution, and the lack of support was a major concern. The team had seriously considered the Tanner toolset a few years ago, and was suitably impressed, but at that time, there was no motivation for change, due to the cost advantage of the corporate high-volume deal with Cadence.
Once the tools were selected, the migration process was carefully planned. Two critical projects were chosen to initiate the switch. One circuit would be simulated and verified on both the Cadence and the Tanner systems simultaneously to compare results, while a second circuit would be designed from scratch on the Tanner suite. Again, a small team was tasked with this effort, then, once they were through the learning curve, the tools would be rolled out to the rest of the group.
The team found that the best time for migration was often just after a design tape out. This generally offered a brief respite from pressure, during which the taped out design could be migrated, and then put through the same qualification tests as for tape out, allowing the team to learn the new tools on familiar circuits, and further increasing confidence in the tooling when the qualification tests gave the same results.
Legacy Safeguard
One of the team's major concerns was the effort that would be involved in moving schematics from the Cadence tools into the Tanner tools. This was important, not just for the first two trial projects, but would be essential for the later migration of other long-running design projects that were part way through, and also for legacy designs, to safeguard traceability and maintain records and documentation currently stored on the Cadence system. The team had some initial pointers from Tanner to get them started. They were pleased to see that the imported designs were immediately readable and usable once imported into the Tanner S-Edit schematic tool. But then they found some problems with the export/import process that required some work before designs could be simulated. It seems that the EDIF standard is not fully defined in some respects, and there were some differences between the Cadence and Tanner implementations of the EDIF. Tanner worked on the changes needed to read the formats correctly, and the issues were resolved within a couple of months.
For simulation, the primary focus was on loading the necessary models into Tanner's T-Spice simulator. These were largely custom models written specifically for the company's novel transistors. The team was impressed with the flexibility and ease of use of the tools, and especially with Tanner's responsiveness in terms of providing custom model support. In fact, they found it took much less time to set up the simulator and de-bug the models with Tanner than it had previously with Cadence. Running the simulation for the first circuit on both simulators ran smoothly, and the engineering team concluded there was good agreement between the results. Confidence in the new tools was running high.
High Speed Response
With the second design proceeding well in the Tanner design environment, there was a slight glitch when a bug was found in the T-Spice simulator. The team had set up a very unusual combination of parameters, which they recognized was probably unique to their design. But Tanner's US-based engineers responded well to the challenge, and managed to send a fix through within two days. This impressed the designers who found Cadence far less responsive to bug reports, taking much longer to admit to bugs, and far longer to fix them.
At the layout stage, migration from Cadence to Tanner was much smoother, primarily because the GDSII standard is far more stable. Once again, the imported layout was immediately visible on the new system running the L-Edit tool. Just a few tweaks were required to interpret a couple of facets of the design. The team was happy with the capability of the layout tools, particularly the interactive design rule checker which displays violations in real-time, and the parasitic extraction facility, both of which are critical for these complex analogue designs.
Comparison of the layout and verification results from the two EDA systems was good, and the design was signed off for fabrication. Both initial designs have now been taped-out; both are 'right first time', operating as expected, and now undergoing further evaluation.
Meanwhile, the Tanner tools were rolled out to other designers in the research group, at appropriate stages of their various projects. The key, the initiating team commented, is to migrate to the new tools when the designers are not under huge pressure, or the project is at a critical stage. Allow time in the project schedule for training. Since then, the legacy design information and schematics have been migrated across, and the Cadence tools have been switched off and stripped out.
In general, the team found the Tanner tools easy to learn and intuitive to use, once the differences in terminology were understood. The designers are particularly encouraged by how easy it is to work with the Tanner tools, and the responsiveness of the vendor. The documentation was effective and the tutorials were useful, the designers found. The two firms are already beginning to talk together about incremental improvements and the future development of the tools. And certainly, following this group's experience, detailed constructive guidance is now available to help others wanting to migrate from Cadence to Tanner.
In terms of methodology, the research team has found a number of unexpected advantages in shifting to the Tanner tool suite. For example, they found there is far more flexibility with a PC-based system, compared to the server-based set up with Cadence. Engineers travelling to other sites or to distant meetings or even moving from the design office to the production department can continue to work directly on the design, making checks and adjustments as necessary.
The Bottom Line
The shift from the Cadence business model of a charge per quarter per tool suite, to the Tanner floating license based approach has not only meant a significant reduction in EDA costs for the group. Previously, the team limited its use of the tools, restricting access to some designers some of the time, because of the additional cost it would incur. With Tanner, all the tools are available at every seat simultaneously. The bottom line according to this group's experience: "90% of the functionality at a fraction of the cost".